Substrate-processing apparatus, substrate-processing method, substrate-processing program, and computer-readable recording medium recorded with such program

ABSTRACT

A pattern forming system  1  includes a checking apparatus  400 , a storage device  502 , and a control section  500 . The checking apparatus  400  is configured to measure and check a state of a resist pattern formed on a substrate W after a developing process and output a first check result thus obtained, and to measure and check a state of a pattern formed on the substrate after an etching process and output a second check result thus obtained. The storage device  502  stores a correlation formula obtained from the first check result and the second check result. The control section  500  is configured to use the correlation formula to obtain a target value of the state of the pattern after the developing process from a target value of the state of the pattern after the etching process, and to use a difference between the target value of the state of the pattern after the developing process and the first check result to set a condition for the first heat process and/or the second heat process.

TECHNICAL FIELD

The present invention relates to a substrate processing system, substrate processing method, substrate processing program, and computer readable storage medium storing the program, for forming a predetermined pattern on a substrate by a photolithography technique.

BACKGROUND ART

In the sequence of photolithography for manufacturing semiconductor devices, the following processes are sequentially performed to form a predetermined resist pattern on a target substrate, such as a semiconductor wafer (which will be referred to as “wafer” hereinafter). Specifically, a resist coating process is performed such that a coating liquid or resist liquid is applied onto the wafer to form a resist film. Then, a pre-baking process (PAB) is performed such that a heat process is performed on the wafer treated by the coating process. Then, a light exposure process is performed such that the resist film is subjected to light exposure in accordance with a predetermined pattern. Then, a post-exposure-baking process (PEB) is performed such that a chemical reaction is promoted in the resist film treated by the light exposure. Then, a developing process is performed such that the resist film treated by the light exposure is developed.

After the photolithography sequence, an etching process is performed such that an underlying film, such as an oxide film, on the wafer is etched by use of the resist pattern as a mask to form a predetermined pattern.

A heat process, such as the pre-baking (PAB) or post-exposure-baking (PEB) described above, is performed in a heat processing unit. The heat processing unit includes a heating plate configured to heat a wafer placed thereon. For example, the heating plate is provided with a heater built therein to emit heat by electric supply, so that the heating plate is heated and adjusted by the heater to a predetermined temperature.

In the heat processing unit, the state of temperature is adjusted by setting, e.g., a heat process temperature, a heat process time, and a temperature increase/decrease value. These process conditions greatly affect the line width (CD) and sidewall angle (SWA) of a resist pattern formed on a wafer, and thus they need to be exactly controlled. The sidewall angle (SWA) means the inclination angle θ1 of a line sidewall, as shown by the sectional view of FIG. 11 that shows a line of a resist pattern.

In order to exactly control the temperature on the surface of a wafer in heating, the heating plate of the heat processing unit is segmented into a plurality of areas, which are respectively provided with independent heaters built therein, so that the temperatures of the heating areas can be respectively adjusted.

In this respect, if the heating areas of the heating plate are controlled by use of the same set temperature, the temperature on the surface of a wafer on the heating plate may become less uniform, due to the difference in thermal resistance between the heating areas, for example. In light of this problem, conventionally, the heating areas of the heating plate are respectively provided with temperature correction values (offset values) for fine adjustment of the temperature on the surface of a wafer. The set temperatures of the heating areas of the heating plate are prepared by correcting the heat process temperature with the respective temperature correction values (for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-143850).

Where the heating areas of the heating plate are respectively provided with temperature correction values, so that the temperature is uniform all over the heating plate, the line width (CD) and sidewall angle (SWA) of a resist pattern are expected to be essentially uniform on the surface of a wafer after a photolithography sequence.

However, even where the line width (CD) and sidewall angle (SWA) of a resist pattern are uniform on a wafer after a photolithography sequence, the line width (CD) and sidewall angle (SWA) of a pattern of an oxide film below the resist pattern may become less uniform after the oxide film is etched by an etching process. This is due to fluctuations of process conditions in the etching process, such as the flow rate of a (etching) gas, which cause a difference in progress of the etching process between the wafer areas respectively corresponding to the heating areas.

DISCLOSURE OF INVENTION

The present invention was made under the circumstances, and has an object to provide a substrate processing system, substrate processing method, substrate processing program, and computer readable storage medium storing the program, which allow the line width (CD) and/or sidewall angle (SWA) of a pattern to be uniform on the surface of a substrate, after an etching process following a photolithography sequence.

According to the present invention, there is provided a substrate processing system for forming a predetermined pattern on a substrate by executing a series of processes, which comprises a coating process for applying a resist liquid onto the substrate with an underlying film formed thereon, a first heat process for performing a heat process on the substrate after the coating process, a light exposure process for performing light exposure on a resist film in accordance with a predetermined pattern, a second heat process for promoting a chemical reaction in the resist film after the light exposure, a developing process for developing the resist film after the light exposure, and an etching process for etching the underlying film by use of a resist pattern formed by the developing process as a mask, the system comprising: a checking apparatus configured to measure and check a state of a resist pattern formed on the substrate after the developing process and output a first check result thus obtained, and to measure and check a state of a pattern formed on the substrate after the etching process and output a second check result thus obtained; a storage device that stores a correlation formula obtained from the first check result and the second check result; and a control section configured to use the correlation formula to obtain a target value of the state of the pattern after the developing process from a target value of the state of the pattern after the etching process, and to use a difference between the target value of the state of the pattern after the developing process and the first check result to set a condition for the first heat process and/or the second heat process.

Process conditions for the first heat process or the second heat process preferably comprise at least a heat process temperature, a heat process time, and a temperature increase/decrease value.

With this arrangement, a correlation formula between a pattern after the developing process and a pattern after the etching process is used to obtain a target value of the pattern after the developing process. Then, a correction value (offset value) to the target value of the pattern after the developing process is fed back to a heat process as a correction value. Consequently, the state of the pattern after the etching process can approximate a target value after the etching process, i.e., it can be uniform on a surface of the substrate.

In the correction described above, the difference between the target value of the state of the pattern after the developing process and the first check result can be converted to a correction value for the heat process in consideration only of process conditions of the sequence up to the developing process. Since the conversion can be performed without considering conditions of the etching process, this operation can be performed easily.

The substrate processing system is preferably arranged such that the system comprises a first heat processing unit configured to perform the first heat process and a second heat processing unit configured to perform the second heat process, each of the first heat processing unit and the second heat processing unit includes a heating plate segmented into a plurality of heating areas and configured to place the substrate on the plurality of heating areas, and heating devices configured to respectively and independently heat the plurality of heating areas, and the checking apparatus is configured to measure and check the state of the pattern after the developing process and the state of the pattern after the etching process, for each of substrate areas of the substrate heat-processed respectively by the plurality of heating areas.

The control section is preferably configured to set a heat process condition for each of the plurality of heating areas of the heating plate.

Where a condition is set on each of the plurality of heating areas, finer adjustment can be performed, so that the state of the pattern can be uniform with higher precision after the etching process.

The substrate processing system is preferably arranged such that the checking apparatus is configured to measure and check a pattern line width and/or a pattern sidewall angle as the state of the pattern, and the control section is configured to perform at least one of setting of a heat process condition for the second heat processing unit so as to cause the pattern line width to approximate a target value thereof after the developing process, and setting of a heat process condition for the first heat processing unit so as to cause the pattern sidewall angle to approximate a target value thereof after the developing process.

Alternatively, the substrate processing system is preferably arranged such that the checking apparatus is configured to measure and check a pattern line width and/or a pattern sidewall angle as the state of the pattern, and the control section is configured to perform at least one of setting of a heat process condition for the first heat processing unit so as to cause the pattern line width to approximate a target value thereof after the developing process, and setting of a heat process condition for the second heat processing unit so as to cause the pattern sidewall angle to approximate a target value thereof after the developing process.

Alternatively, the substrate processing system is preferably arranged such that the checking apparatus is configured to measure and check a pattern line width or a pattern sidewall angle as the state of the pattern, and the control section is configured to set a heat process condition for the first heat processing unit and the second heat processing unit so as to cause the pattern line width or the pattern sidewall angle to approximate a target value thereof after the developing process.

With this arrangement, optimum conditions can be set, i.e., offset (correction) values can be set, respectively for the pattern line width and sidewall angle to uniformize the pattern line width and sidewall angle on the surface of the substrate after the etching process.

According to the present invention, there is provided a substrate processing method for forming a predetermined pattern on a substrate by executing a series of processes, which comprises a coating process for applying a resist liquid onto the substrate with an underlying film formed thereon, a first heat process for performing a heat process on the substrate after the coating process, a light exposure process for performing light exposure on a resist film in accordance with a predetermined pattern, a second heat process for promoting a chemical reaction in the resist film after the light exposure, a developing process for developing the resist film after the light exposure, and an etching process for etching the underlying film by use of a resist pattern formed by the developing process as a mask, the method comprising: measuring and checking a state of a resist pattern formed on the substrate after the developing process and outputting a first check result thus obtained; measuring and checking a state of a pattern formed on the substrate after the etching process and outputting a second check result thus obtained; using a correlation formula obtained from the first check result and the second check result to obtain a target value of the state of the pattern after the developing process from a target value of the state of the pattern after the etching process; and using a difference between the target value of the state of the pattern after the developing process and the first check result to set a condition for the first heat process and/or the second heat process so as to cause the state of the pattern after the etching process to be uniform on a surface of the substrate in a subsequent series of processes.

Process conditions for the first heat process or the second heat process preferably comprise at least a heat process temperature, a heat process time, and a temperature increase/decrease value.

With this arrangement, a correlation formula between a pattern after the developing process and a pattern after the etching process is used to obtain a target value of the pattern after the developing process. Then, a correction value (offset value) to the target value of the pattern after the developing process is fed back to a heat process as a correction value. Consequently, the state of the pattern after the etching process can approximate a target value after the etching process, i.e., it can be uniform on a surface of the substrate.

In the correction described above, the difference between the target value of the state of the pattern after the developing process and the first check result can be converted to a correction value for the heat process in consideration only of process conditions of the sequence up to the developing process. Since the conversion can be performed without considering conditions of the etching process, this operation can be performed easily.

The substrate processing method is preferably arranged such that the state of the pattern measured and checked is a pattern line width and/or a pattern sidewall angle, and the method comprises setting a condition for the first heat process and/or the second heat process by performing at least one of setting of a condition for the second heat process so as to cause the pattern line width to approximate a target value thereof after the developing process, and setting of a condition for the first heat process so as to cause the pattern sidewall angle to approximate a target value thereof after the developing process.

Alternatively, the substrate processing method is preferably arranged such that the state of the pattern measured and checked is a pattern line width and/or a pattern sidewall angle, and the method comprises setting a condition for the first heat process and/or the second heat process by performing at least one of setting of a condition for the first heat process so as to cause the pattern line width to approximate a target value thereof after the developing process, and setting of a condition for the second heat process so as to cause the pattern sidewall angle to approximate a target value thereof after the developing process.

Alternatively, the substrate processing method is preferably arranged such that the state of the pattern measured and checked is a pattern line width or a pattern sidewall angle, and the method comprises setting a condition for the first heat process and/or the second heat process by setting a condition for the first heat process and the second heat process so as to cause the pattern line width or the pattern sidewall angle to approximate a target value thereof after the developing process.

With this arrangement, optimum conditions can be set, i.e., offset (correction) values can be set, respectively for the pattern line width and sidewall angle to uniformize the pattern line width and sidewall angle on the surface of the substrate after the etching process.

According to the present invention, there is provided a substrate processing program for execution on a computer, wherein the control program, when executed, causes the computer to control a substrate processing system to perform a substrate processing method for forming a predetermined pattern on a substrate by executing a series of processes, which comprises a coating process for applying a resist liquid onto the substrate with an underlying film formed thereon, a first heat process for performing a heat process on the substrate after the coating process, a light exposure process for performing light exposure on a resist film in accordance with a predetermined pattern, a second heat process for promoting a chemical reaction in the resist film after the light exposure, a developing process for developing the resist film after the light exposure, and an etching process for etching the underlying film by use of a resist pattern formed by the developing process as a mask, the method comprising: measuring and checking a state of a resist pattern formed on the substrate after the developing process and outputting a first check result thus obtained; measuring and checking a state of a pattern formed on the substrate after the etching process and outputting a second check result thus obtained; using a correlation formula obtained from the first check result and the second check result to obtain a target value of the state of the pattern after the developing process from a target value of the state of the pattern after the etching process; and using a difference between the target value of the state of the pattern after the developing process and the first check result to set a condition for the first heat process and/or the second heat process so as to cause the state of the pattern after the etching process to be uniform on a surface of the substrate in a subsequent series of processes.

According to the present invention, there is provided a computer readable storage medium that stores the substrate processing program described above.

According to the present invention, there is provided a substrate processing system, substrate processing method, substrate processing program, and computer readable storage medium storing the program, which allow the pattern line width (CD) and sidewall angle (SWA) to be uniform on the surface of a substrate after an etching process following a photolithography sequence.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 This is a plan view schematically showing the structure of a pattern forming system, which is a substrate processing system according to the present invention.

FIG. 2 This is a front view of the coating/developing apparatus shown in FIG. 1.

FIG. 3 This is a back view of the coating/developing apparatus shown in FIG. 1.

FIG. 4 This is a view schematically showing the structure of the heating plate of a heat processing unit used in the coating/developing apparatus shown in FIG. 1.

FIG. 5 This is a sectional view schematically showing a checking apparatus used in the pattern forming system shown in FIG. 1.

FIG. 6 This is a sectional view showing a main part of a checking machine.

FIG. 7 This is a view showing the areas of a wafer respectively corresponding to the heating areas of the heating plate.

FIG. 8 This is a view for explaining a formula for calculating the sidewall angle.

FIG. 9 This is a diagram showing an example of a reference table with offset values recorded therein.

FIG. 10 This is a flow chart showing a flow of control for correcting heat process conditions used in the pattern forming system.

FIG. 11 This is a view for explaining the sidewall angle.

BEST MODE FOR CARRYING OUT THE INVENTION

A substrate processing system, substrate processing method, substrate processing program, and computer readable storage medium storing the program, according to the present invention, will now be described with reference to an embodiment shown in the accompanying drawings. FIG. 1 is a plan view schematically showing the structure of a pattern forming system 1, which is a substrate processing system according to the present invention.

The pattern forming system 1 shown in FIG. 1 includes a coating/developing apparatus 100 used for performing resist liquid coating, heating, and developing processes on a target substrate or semiconductor wafer, a light exposure apparatus 200 for performing a light exposure process on the wafer, and an etching apparatus 300 for performing a predetermined etching process on the substrate after the developing process.

The system further includes a checking apparatus 400 for measuring and checking the line width (CD) and sidewall angle (SWA) of a pattern after the etching process performed by the etching apparatus 300. The respective apparatuses are controlled as a whole by a control section 500 comprising a multi-purpose computer including an operation part (CPU) and a storage part (memory).

At first, a brief explanation will be given of the coating/developing apparatus 100 with reference to FIGS. 1 to 3. FIG. 2 is a front view of the coating/developing apparatus 100 shown in FIG. 1. FIG. 3 is a back view of the coating/developing apparatus 100 shown in FIG. 1.

As shown in FIG. 1, the coating/developing apparatus 100 includes a cassette station 2, a process station 3, and an interface section 4 integratedly connected to each other. The cassette station 2 is used such that wafer cassettes, each storing, e.g., 25 wafers W, are transferred to and from external systems therethrough, and wafers W are transferred to and from cassettes C placed thereon. The process station 3 comprises a plurality of processing units stacked one on the other and configured to perform predetermined processes on wafers one by one in a photolithography sequence. The interface section 4 is disposed adjacent to the process station 3 and configured to transfer wafers W to and from the light exposure apparatus 200.

The cassette station 2 includes a cassette table 5, on which a plurality of cassettes C can be placed in a row in an X-direction (the vertical direction in FIG. 1). The cassette station 2 is provided with a wafer transfer member 7 movable on a guide rail 6 in the X-direction. The wafer transfer member 7 is also movable in the array direction of wafers W stored in each cassette C (Z-direction or vertical direction), so that it can selectively access the wafers W in the cassettes arrayed in the X-direction.

Further, the wafer transfer member 7 is rotatable in a θ-direction about the Z axis, so that it can access a temperature adjusting unit 60 and a transit unit 61 disposed in a third processing unit group G3 inside the process station 3, as described later.

The process station 3 adjacent to the cassette station 2 includes, e.g., five processing unit groups G1 to G5 each comprising a plurality of processing units stacked one on the other.

Specifically, as shown on the lower side of FIG. 1, the process station 3 includes a first processing unit group G1 and a second processing unit group G2 arrayed in this order from the cassette station 2. Further, as shown on the upper side of FIG. 1, the process station 3 includes a third processing unit group G3, a fourth processing unit group G4, and a fifth processing unit group G5 arrayed in this order from the cassette station 2.

A first transfer unit 10 is disposed between the third processing unit group G3 and fourth processing unit group G4. The first transfer unit 10 can selectively access the processing units in the first processing unit group G1, third processing unit group G3, and fourth processing unit group G4 to transfer wafers W to and from these units.

A second transfer unit 11 is disposed between the fourth processing unit group G4 and fifth processing unit group G5. The second transfer unit 11 can selectively access the processing units in the second processing unit group G2 and fifth processing unit group G5 to transfer wafers W to and from these units.

As shown in FIG. 2, the first processing unit group G₁ includes five liquid processing units stacked one on the other, each for performing a process on a wafer W while supplying a predetermined liquid thereon. These units are formed of, e.g., resist coating units (COT) 20, 21, and 22 each for applying a resist liquid onto a wafer W and bottom coating units (BARC) 23 and 24 each for forming an anti-reflective coating that prevents reflection of light during a light exposure process, which are stacked in this order from below. The second processing unit group G2 includes five liquid processing units stacked one on the other, which are formed of, e.g., developing units (DEV) 30 to 34 stacked in this order from below, each for performing a developing process on a wafer W while supplying a developing liquid thereon.

Further, chemical chambers (CHM) 35 and 36 are respectively disposed below the first processing unit group G1 and second processing unit group G2 and are used for supplying various process liquids to the liquid processing units located in the processing unit groups G1 and G2.

As shown in FIG. 3, the third processing unit group G3 includes nine processing units stacked one on the other. These units are formed of, e.g., a temperature adjusting unit (TCP) 60, a transit unit (TRS) 61 through which wafers W are transferred, high-precision temperature adjusting units (CPL) 62 to 64 each for adjusting the temperature of a wafer W by temperature control with high precision, and high-temperature heat processing units (BAKE) 65 to 68 each for performing a heat process on a wafer W at a high temperature, which are stacked in this order from below.

The fourth processing unit group G4 includes ten processing units stacked one on the other. These units are formed of, e.g., a high-precision temperature adjusting unit (CPL) 70, pre-baking units (PAB/first heat processing units) 71 to 74 each for performing a heat process (first heat process) on a wafer W after a resist coating process, and post baking units (POST) 75 to 79 each for performing a heat process on a wafer W after a developing process, which are stacked in this order from below.

The fifth processing unit group G5 includes ten heat processing units stacked one on the other, each for performing a heat process on a wafer W. These units are formed of, e.g., high-precision temperature adjusting units (CPL) 80 to 83 and post-exposure-baking units (PEB/second heat processing units) 84 to 89 each for performing a heat process (second heat process) on a wafer W after light exposure, which are stacked in this order from below.

A plurality of, such as four, processing units are disposed on the forward side of the first transfer unit 10 in the X-direction. As shown in FIG. 3, these units are formed of, e.g., adhesion units (AD) 90 and 91 each for performing a hydrophobic process on a wafer W and heating units (HP) 92 and 93 each for heating a wafer W, which are stacked in this order from below.

A periphery light exposure unit (WEE) 94 is disposed on the forward side of the second transfer unit 11 in the X-direction, for performing light exposure selectively only on the edge portion of a wafer W, for example.

Each of the heat processing units, such as the pre-baking units (PAB) 71 to 74 and post-exposure-baking units (PEB) 84 to 89, includes a heating plate 140, as shown in FIG. 4.

The heating plate 140 is segmented into a plurality of, such as five, heating areas R1, R2, R3, R4, and R5, as shown in FIG. 4. Specifically, for example, the heating plate 140 is formed of a circular heating area R1 located at the center and four arched heating areas R2 to R5 equally dividing the annular shape around the area R1.

The heating areas R1 to R5 of the heating plate 140 are respectively provided with heating devices or heaters 141 that emit heat by electric supply, so that the heating areas R1 to R5 are independently heated. The heat-emitting amounts of the heaters 141 of the heating areas R1 to R5 are adjusted by a temperature control unit 142 provided to each of the heat processing units. The temperature control unit 142 is configured to adjust the heat-emitting amounts of the heaters 141, so as to control the temperatures of the heating areas R1 to R5 to predetermined temperatures. The temperature setting of the temperature control unit 142 is controlled by the control section 500.

As shown in FIG. 1, the interface section 4 includes a wafer transfer member 41 movable on a guide rail 40 extending in the X-direction, and a buffer cassette 42. The wafer transfer member 41 is movable in the Z-direction and rotatable in a θ-direction, so that it can access the light exposure apparatus 200 adjacent to the interface section 4, buffer cassette 42, and fifth processing unit group G5 to transfer wafers W to and from these portions.

The light exposure apparatus 200 is configured to irradiate a wafer W having a resist liquid applied thereon with predetermined light rays from a light exposure section (not shown) through a predetermined mask pattern. The light exposure section includes a light source, a lens, an optical fiber, and so forth.

Light exposure conditions used in the light exposure apparatus 200 are determined by light exposure intensity, light exposure time, light exposure focus, and light exposure alignment position. These parameters are controlled by a controller 210 for controlling the light exposure apparatus 200 as a whole, in accordance with instructions from the control section 500.

Next, an explanation will be given of the flow of a photolithography sequence until a developing process, performed by the coating/developing apparatus 100 and light exposure apparatus 200 having the structures described above.

At first, one of the unprocessed wafers W stored in a cassette C on the cassette station 2 is transferred by the wafer transfer member 7 into the transit unit (TRS) 61 in the third processing unit group G3. After subjected to alignment, the wafer W is transferred into one of the adhesion units (AD) 90 and 91, in which a hydrophobic process is performed on the wafer W. Then, the wafer W is subjected to a predetermined cooling process in one of the high-precision temperature adjusting units (CPL) 62 to 64. Then, the wafer W is transferred into one of the resist coating units (COT) 20 to 22 in the first processing unit group G1, in which a resist coating process is performed on the surface of the wafer W. At this time, transfer of the wafer W from the transit unit 61 to one of the resist coating units (COT) 20 to 22 is performed by the first transfer unit 10.

Then, the wafer W is transferred by the first transfer unit 10 into one of the pre-baking units (PAB) 71 to 74 in the fourth processing unit group G4, in which a predetermined heat process or pre-baking process is performed on the wafer W. After the pre-baking, the wafer W is transferred into the periphery light exposure unit (WEE) 94, in which a light exposure process is performed only on the edge portion of the wafer W.

Thereafter, the wafer W is subjected to a cooling process in one of the high-precision temperature adjusting units (CPL) 80 to 83. Then, the wafer W is temporarily stored into the buffer cassette 42 by the wafer transfer member 41 of the interface section 4.

The wafer W temporarily stored in the buffer cassette 42 is then taken out by the wafer transfer member 41 and transferred to the light exposure apparatus 200, in which a predetermined light exposure process is performed on the wafer W.

After the light exposure process, the wafer W is transferred through the interface section 4 into one of the post-exposure-baking units (PEB) 84 to 89 in the fifth processing unit group G5, in which a post-exposure heat process is performed on the wafer W.

Then, the wafer W is transferred by the second transfer unit 11 into one of the developing processing units 30 to 34 in the second processing unit group G2, in which a developing process is performed on the wafer W. Then, the wafer W is transferred into one of the post baking units (POST) 75 to 79 in the fourth processing unit group G4, in which a post-development heat process is performed on the wafer W. Then, the wafer W is subjected to a cooling process in one of the high-precision temperature adjusting units (CPL) 62 to 64 in the third processing unit group G3. Then, the wafer W is transferred by the wafer transfer member 7 back to a cassette C.

Next, the etching apparatus 300 will be explained. The etching apparatus 300 is used for a wafer W after a photolithography sequence is performed thereon by the coating/developing apparatus 100 and light exposure apparatus 200. The etching apparatus 300 is configured to perform an etching process for etching an underlying film on the wafer W, such as an Si oxide film, while using as a mask a resist pattern formed as described above. For this process, after the wafer W is subjected to the developing process and returned to a cassette C in the coating/developing apparatus 100, the wafer W is transferred by a transfer unit (not shown) to the checking apparatus 400, in which the wafer W is checked, and then the wafer W is transferred to the etching apparatus 300.

For example, the etching apparatus 300 is configured to generate plasma of a predetermined etching gas by a plasma generator of the parallel plate type, and thereby to perform a predetermined plasma process on the wafer W.

Etching conditions used in the etching apparatus 300 can be determined by etching time and/or etching gas composition ratio. The etching time is defined by a time for which the etching gas is supplied onto the wafer W. The etching gas composition ratio can be determined by the type and amount of the etching gas. These parameters are controlled by a controller 310 for controlling the etching apparatus 300 as a whole, in accordance with instructions from the control section 500.

Next, an explanation will be given of the checking apparatus 400, with reference to FIGS. 1, 5, and 6. FIG. 5 is a sectional view schematically showing the checking apparatus. FIG. 6 is a sectional view showing a main part of a checking machine.

For example, as shown in FIG. 1, the checking apparatus 400 includes a casing 401, in which an I/O stage 403, a checking unit 402, and an auxiliary arm 404 are disposed. The I/O stage 403 is used for transferring therethrough a cassette with wafers W stored therein. The auxiliary arm 404 is movable up and down, movable in the X- and Y-directions, and rotatable about a vertical axis, so that it serves as an auxiliary substrate transfer device dedicated to transfer of wafers W between the I/O stage 403 and checking unit 402.

After a wafer W is subjected to the developing process and returned to a cassette C in the coating/developing apparatus 100, the wafer W is transferred by a transfer mechanism (not shown) to the checking apparatus 400, in which the wafer W is checked. Then, the wafer W is transferred to the etching apparatus 300, in which an etching process is performed. Then, the wafer W is transferred to the checking apparatus 400 again, in which the wafer W is checked.

In this flow, when the wafer W is transferred to the checking apparatus 400, the wafer W is stored into the cassette on the I/O stage 403.

For example, in this embodiment, as shown in FIG. 5, the checking unit 402 includes a plurality of, such as two, checking machines, i.e., a CD checking machine 402 a and an SWA checking machine 402 b. The CD checking machine 402 a is configured to measure the line width (CD) of a pattern formed on a wafer W. The SWA checking machine 402 b is configured to measure the sidewall angle (SWA) of a pattern.

Each of the CD checking machine 402 a and SWA checking machine 402 b performs a predetermined check while picking up an image by, e.g., a CCD camera. An example of these machines will be explained with reference to FIG. 6.

For example, each of these checking machines includes a casing 405 having a transfer port (not shown) for a wafer W, in which a rotary table 406, a CCD camera 407, and a lighting device 408 are disposed. The rotary table 406 is configured to support a wafer W in a horizontal state and adjust the orientation thereof. The CCD camera 407 is movable in the X-, Y-, and Z-directions and configured to pick up an image of the wafer W on the rotary table 406. An image of the wafer W picked up by the CCD camera 407 is analyzed and checked by a computer 409 or the like serving as a data processor.

The computer 409 serves to control traveling of the CCD camera 407 and to transmit measurement data to the control section 500. The CCD camera 407 may be set stationary while the table 406 for a wafer W is movable in the X-, Y-, and Z-directions.

In the CD checking machine 402 a according to the structure described above, a wafer W is checked for each of predetermined areas (substrate areas) A1 to A5 thereof, as shown in FIG. 7, for example. Based on picked-up images of these areas, the computer 409 calculates values of the TCD (top critical dimension), BCD (bottom critical dimension), and pattern thickness of lines of a pattern formed by a photolithography sequence, as shown in the sectional view of FIG. 8, and then transmits the results to the control section 500.

The areas A1 to A5 of the wafer W shown in FIG. 7 respectively correspond to the heating areas R1 to R5 of the heating plate 140 shown in FIG. 4, disposed in each of the pre-baking units (PAB) 71 to 74 and post-exposure-baking units (PEB) 84 to 89.

In the SWA checking machine 402 b, based on values of the TCD, BCD, and pattern thickness obtained by the CD checking machine 402 a, the computer 409 calculates the sidewall angle θ1 for each of the areas A1 to A5 of the wafer W shown in FIG. 7, in accordance with Formula 1, and then transmits the results to the control section 500.

$\begin{matrix} {{{Tan}\;{\theta 1}} = \frac{{Pattern}\mspace{14mu}{thickness}}{1\text{/}2 \times \left( {{BCD} - {TCD}} \right)}} & \left( {{Formula}\mspace{14mu} 1} \right) \end{matrix}$

As described above, the checking apparatus 400 is used to obtain the line width (CD) and sidewall angle (SWA) of a pattern after the photolithography sequence and a pattern after the etching process. In the following explanation, in order to discriminate a check result (first check result) after the photolithography sequence and a check result (second check result) after the etching process from each other, a pattern line width and a sidewall angle after the photolithography sequence are respectively denoted by CDp and SWAp, and a pattern line width and a sidewall angle after the etching process are respectively denoted by CDe and SWAe.

As shown in FIG. 1, the control section 500 comprises an operation part 501 for executing programs and performing various calculations, a storage device 502, and so forth. The storage device 502 stores a program P for performing a pattern forming process including a flow of a photolithography sequence, a sub-program SP for deriving correction values (offset values) for heat processes, a reference table T described later, and a plurality of process recipe data with process conditions set therein. The sub-program SP includes a correlation formula representing the relation between CDp and SWAp after the photolithography sequence and CDe and SWAe after the etching process.

In the control section 500, the storage device 502 storing the program P, sub-program SP, and so forth may comprise a storage medium, such as a hard disk, nonvolatile memory, and/or detachable storage medium (for example, an optical disk or memory card).

After the control section 500 receives measurement results from the checking unit 402, the control section 500 executes the sub-program SP to obtain the differences ΔCDp and ΔSWAp respectively between the pattern line width (CD) and sidewall angle (SWA) thus measured and the target pattern line width (target CDp) and target sidewall angle (target SWAp) after the photolithography sequence, for each of the areas A1 to A5 of the wafer W. Then, the control section 500 obtains correction values, such as temperature offset values, in accordance with the differences ΔCDp and ΔSWAp.

For the target pattern line width (target CDp), and the pattern line width (CDp, CDe) measured by the checking unit 402, either one of TCD and BCD can be applied. In this embodiment, however, BCD is used for this purpose.

As a method for obtaining a correction value, such as a temperature offset value, from the differences ΔCDp and ΔSWAp, the control section 500 utilizes a reference table T stored in the storage device 502, as shown in FIG. 9, for example.

The reference table T includes correction values (offset values) for heat process conditions, such as temperature offset values, optimum to the differences ΔCDp and ΔSWAp, which are set in advance respectively for the heating areas R1 to R5 in each of the pre-baking units (PAB) 71 to 74 and post-exposure-baking units (PEB) 84 to 89.

The heat process conditions described above include at least a heat process temperature, a heat process time, and a temperature increase/decrease value.

Where these offset values are applied, a resist pattern is formed with dimensions approximating the target pattern line width (target CDp) and target sidewall angle (target SWAp) in each of the areas A1 to A5 of the wafer W after the photolithography sequence.

Where correction values (offset values), such as temperature offset values, based on ΔCDp described above are applied to the pre-baking units (PAB) 71 to 74, correction values (offset values), such as temperature offset values, based on ASWAP described above are applied to the post-exposure-baking units (PEB) 84 to 89.

Alternatively, where correction values (offset values), such as temperature offset values, based on ΔCDp described above are applied to the post-exposure-baking units (PEB) 84 to 89, correction values (offset values), such as temperature offset values, based on ΔSWAp described above are applied to the pre-baking units (PAB) 71 to 74.

With the operation described above, optimum offset (correction) values can be set to cause the line width (CDp) and sidewall angle (SWAp) of a pattern after the photolithography sequence to respectively approximate the target values. Consequently, the line width (CDe) and sidewall angle (SWAe) of a pattern become uniform on the surface of a wafer after the etching process.

Next, an explanation will be given of a flow of control for correcting heat process conditions used in the pattern forming system 1 having the structure described above, with reference to the flow chart of FIG. 10.

At first, the program P is executed to start a photolithography sequence (step S1 in FIG. 10).

After the photolithography sequence is finished and a resist pattern is formed, the wafer W is transferred to the checking apparatus 400, in which the pattern line width (CDp) and sidewall angle (SWAp) are measured (step S2 in FIG. 10). The measurement data is output to the control section 500.

Then, the wafer W is transferred to the etching apparatus 300, in which an etching process is performed (step S3 in FIG. 10).

Then, the wafer W is transferred to the checking apparatus 400 again, in which the pattern line width (CDe) and sidewall angle (SWAe) are measured (step S4 in FIG. 10). The measurement data is output to the control section 500.

The operation part 501 of the control section 500 calculates the differences ΔCDe and ΔSWAe respectively between CDe and SWAe measured in the step S4 and the target pattern line width (target CDe) and target sidewall angle (target SWAe) after the etching process, for each of the areas A1 to A5 of the wafer W (step S5 in FIG. 10).

Then, a judgment is made of whether or not each of the differences ΔCDe and ΔSWAe obtained in the step S5 for the respective areas is within a specification range that delimits a state of each of CD and SWA deemed as being essentially uniform on the surface of a wafer W (step S6 in FIG. 10). Where this dimension is within the specification range (Yes), no correction is applied to the next photolithography sequence.

On the other hand, where ΔCDe or ΔSWAe in any one of the areas A1 to A5 is out of the specification range (No) in the step S6, a correction value (offset value) used in the heat process is calculated for the problematic area so that correction can be applied to the next photolithography sequence.

When the correction value (offset value) is derived, the sub-program SP is executed under the program P. The sub-program SP employs Correlation formula 1 stored in the storage device 502.

This Correlation formula 1 represents the correlation between the line width (CDp) and sidewall angle (SWAp) of a pattern after the photolithography sequence and the line width (CDe) and sidewall angle (SWAe) of a pattern after the etching process, and is expressed, as follows, for example. CDe=a×CDp+b×SWAp+c×TH  (Correlation formula 1)

[Where a, b, and c denotes coefficients, and TH denotes the film thickness of an etching target layer]

When the sub-program SP is executed, at first, Correlation formula 1 is used to calculate the target line width (target CDp) and target sidewall angle (target SWAp) of the pattern after the photolithography sequence (step S7 in FIG. 10).

The target values after the photolithography sequence thus obtained are not necessarily uniform among the areas A1 to A5 of the wafer W.

Then, the differences ΔCDp and ΔSWAp between the target CDp and target SWAp and the CDp and SWAp measured in the step S2 are respectively calculated (step S8 in FIG. 10).

Then, the differences ΔCDp and ΔSWAp are used to calculate correction values, such as temperature offset values, (offset values, such as ΔPAB temperature and ΔPEB temperature) with reference to the reference table T (step S9 in FIG. 10).

Then, a judgment is made of whether or not each of the correction values (offset values) thus derived is within a range that delimits its state settable as an offset value in the pre-baking units (PAB) 71 to 74 and post-exposure-baking units (PEB) 84 to 89 (step S10 in FIG. 10).

Where a correction value is settable as an offset value, (Yes) in step S10, this correction value is output to the temperature control unit 142 as a parameter, in accordance with the sub-program SP. Hence, the program is completed. The setting temperatures of the heating areas R1 to R5 of the heating plate 140 are adjusted in accordance with the correction values (offset values) thus fed back (step S11 in FIG. 10).

In the next photolithography sequence or thereafter, the line width (CDp) and sidewall angle (SWAp) of a pattern are caused to respectively approximate the target CDp and target SWAp in each of the areas A1 to A5 of the wafer W. Consequently, it is possible to form a pattern with a line width (CDe) and a sidewall angle (SWAe) uniform over the areas A1 to A5 of the wafer W after the etching process

Where a correction value (offset value) derived as described above is not settable as an offset value in the pre-baking units (PAB) 71 to 74 and post-exposure-baking units (PEB) 84 to 89, (No) in step S10, a warning, such as an alarm, is raised (step S12 in FIG. 10).

As described above, according to the embodiment of the present invention, a correlation formula in the line width (CD) and sidewall angle (SWA) between a pattern after the photolithography sequence and a pattern after the etching process is used to obtain a target CD and a target SWA of the pattern after the photolithography sequence. Then, correction values (offset values) to the target values of the pattern after the photolithography sequence are fed back to the heat process as correction values. Consequently, the line width (CD) and sidewall angle (SWA) of the pattern after the etching process can always become uniform on the surface of the wafer.

In the correction described above, the reference table T for converting ΔCDp and ΔSWAp to offset values, such as temperatures, can be fabricated in consideration only of process conditions of the photolithography sequence. Since the reference table T can be fabricated without considering conditions of the etching process, this fabrication can be performed easily.

The embodiment described above is intended only to clarify the technical content of the present invention, and, therefore, the present invention should not be construed as being limited to the embodiment. Various modifications may be made without departing from the spirit of the present invention or the scope of the appended claims.

For example, in the embodiment described above, optimum correction values (offset values) are set to cause the line width (CDp) and sidewall angle (SWAp) of a pattern after the photolithography sequence to respectively approximate target values. Consequently, the line width (CDe) and sidewall angle (SWAe) of a pattern after the etching process become uniform on the surface of a wafer. However, the present invention is not limited to this example.

For example, there may be a case where an optimum correction value (offset value) needs to be set to a target value of a pattern after the photolithography sequence, only for the line width (CD). In this case, a correlation formula between the pattern after the photolithography sequence and a pattern after the etching process is used to obtain a target CD of the pattern after the photolithography sequence.

Thereafter, in this case, a correction value (offset value), such as a temperature offset value, based only on ΔCDp is applied to at least one of the pre-baking units (PAB) 71 to 74 or post-exposure-baking units (PEB) 84 to 89. Consequently, the line width (CDe) of the pattern after the subsequent etching process can be uniform on the surface of the wafer.

Similarly, for example, there may be a case where an optimum correction value (offset value) needs to be set to a target value of a pattern after the photolithography sequence, only for the sidewall angle (SWA). In this case, a correlation formula between the pattern after the photolithography sequence and a pattern after the etching process is used to obtain a target SWA of the pattern after the photolithography sequence.

Thereafter, in this case, a correction value (offset value), such as a temperature offset value, based only on ΔSWAp is applied to at least one of the pre-baking units (PAB) 71 to 74 or post-exposure-baking units (PEB) 84 to 89. Consequently, the sidewall angle (SWAe) of the pattern after the subsequent etching process can be uniform on the surface of the wafer.

In the embodiment described above, the heating face of the heating plate 140 is segmented into five areas R1 to R5, and the wafer face (substrate face) is also formed of five areas A1 to A5 corresponding to the five areas R1 to R5. However, this is not limiting, and the number of areas may be more than five, for example.

In the embodiment described above, as shown in FIG. 1, the checking apparatus 400 and control section 500 are disposed independently of the coating/developing apparatus 100. However, this is not limiting, and the checking apparatus 400 and/or control section 500 may be incorporated in the coating/developing apparatus 100, as needed. In this case, the occupancy area (foot print) of the apparatus can be smaller in a clean room.

In the embodiment described above, the target substrate is exemplified by a semiconductor wafer, but the present invention may be applied to a substrate other than the semiconductor wafer, such as an LCD substrate, CD substrate, glass substrate, photo mask, or printed board.

INDUSTRIAL APPLICABILITY

The present invention is applicable to, e.g., a pattern forming system for forming a predetermined pattern on a substrate, such as a semiconductor wafer, by a photolithography technique, and is preferably used in the semiconductor manufacturing field, electronic device manufacturing field, and so forth. 

1. A substrate processing system for forming a predetermined pattern on a substrate by executing a series of processes, which comprises a coating process for applying a resist liquid onto the substrate with an underlying film formed thereon, a first heat process for performing a heat process on the substrate after the coating process, a light exposure process for performing light exposure on a resist film in accordance with a predetermined pattern, a second heat process for promoting a chemical reaction in the resist film after the light exposure, a developing process for developing the resist film after the light exposure, and an etching process for etching the underlying film by use of a resist pattern formed by the developing process as a mask, the system comprising: a checking apparatus configured to measure and check a state of a resist pattern formed on the substrate after the developing process and output a first check result thus obtained, and to measure and check a state of a pattern formed on the substrate after the etching process and output a second check result thus obtained; a storage device that stores a correlation formula obtained from the first check result and the second check result; and a control section configured to use the correlation formula to obtain a target value of the state of the pattern after the developing process from a target value of the state of the pattern after the etching process, and to use a difference between the target value of the state of the pattern after the developing process and the first check result to set a condition for the first heat process and/or the second heat process.
 2. The substrate processing system according to claim 1, wherein the system comprises a first heat processing unit configured to perform the first heat process and a second heat processing unit configured to perform the second heat process, each of the first heat processing unit and the second heat processing unit includes a heating plate segmented into a plurality of heating areas and configured to place the substrate on the plurality of heating areas, and heating devices configured to respectively and independently heat the plurality of heating areas, and the checking apparatus is configured to measure and check the state of the pattern after the developing process and the state of the pattern after the etching process, for each of substrate areas of the substrate heat-processed respectively by the plurality of heating areas.
 3. The substrate processing system according to claim 2, wherein the control section is configured to set a heat process condition for each of the plurality of heating areas of the heating plate.
 4. The substrate processing system according to claim 1, wherein the checking apparatus is configured to measure and check a pattern line width and/or a pattern sidewall angle as the state of the pattern, and the control section is configured to perform at least one of setting of a heat process condition for the second heat processing unit so as to cause the pattern line width to approximate a target value thereof after the developing process, and setting of a heat process condition for the first heat processing unit so as to cause the pattern sidewall angle to approximate a target value thereof after the developing process.
 5. The substrate processing system according to claim 1, wherein the checking apparatus is configured to measure and check a pattern line width and/or a pattern sidewall angle as the state of the pattern, and the control section is configured to perform at least one of setting of a heat process condition for the first heat processing unit so as to cause the pattern line width to approximate a target value thereof after the developing process, and setting of a heat process condition for the second heat processing unit so as to cause the pattern sidewall angle to approximate a target value thereof after the developing process.
 6. The substrate processing system according to claim 1, wherein the checking apparatus is configured to measure and check a pattern line width or a pattern sidewall angle as the state of the pattern, and the control section is configured to set a heat process condition for the first heat processing unit and the second heat processing unit so as to cause the pattern line width or the pattern sidewall angle to approximate a target value thereof after the developing process.
 7. The substrate processing system according to claim 1, wherein process conditions for the first heat process or the second heat process comprise at least a heat process temperature, a heat process time, and a temperature increase/decrease value.
 8. A substrate processing method for forming a predetermined pattern on a substrate by executing a series of processes, which comprises a coating process for applying a resist liquid onto the substrate with an underlying film formed thereon, a first heat process for performing a heat process on the substrate after the coating process, a light exposure process for performing light exposure on a resist film in accordance with a predetermined pattern, a second heat process for promoting a chemical reaction in the resist film after the light exposure, a developing process for developing the resist film after the light exposure, and an etching process for etching the underlying film by use of a resist pattern formed by the developing process as a mask, the method comprising: measuring and checking a state of a resist pattern formed on the substrate after the developing process and outputting a first check result thus obtained; measuring and checking a state of a pattern formed on the substrate after the etching process and outputting a second check result thus obtained; using a correlation formula obtained from the first check result and the second check result to obtain a target value of the state of the pattern after the developing process from a target value of the state of the pattern after the etching process; and using a difference between the target value of the state of the pattern after the developing process and the first check result to set a condition for the first heat process and/or the second heat process so as to cause the state of the pattern after the etching process to be uniform on a surface of the substrate in a subsequent series of processes.
 9. The substrate processing method according to claim 8, wherein the state of the pattern measured and checked is a pattern line width and/or a pattern sidewall angle, and the method comprises setting a condition for the first heat process and/or the second heat process by performing at least one of setting of a condition for the second heat process so as to cause the pattern line width to approximate a target value thereof after the developing process, and setting of a condition for the first heat process so as to cause the pattern sidewall angle to approximate a target value thereof after the developing process.
 10. The substrate processing method according to claim 8, wherein the state of the pattern measured and checked is a pattern line width and/or a pattern sidewall angle, and the method comprises setting a condition for the first heat process and/or the second heat process by performing at least one of setting of a condition for the first heat process so as to cause the pattern line width to approximate a target value thereof after the developing process, and setting of a condition for the second heat process so as to cause the pattern sidewall angle to approximate a target value thereof after the developing process.
 11. The substrate processing method according to claim 8, wherein the state of the pattern measured and checked is a pattern line width or a pattern sidewall angle, and the method comprises setting a condition for the first heat process and/or the second heat process by setting a condition for the first heat process and the second heat process so as to cause the pattern line width or the pattern sidewall angle to approximate a target value thereof after the developing process.
 12. The substrate processing method according to claim 8, wherein process conditions for the first heat process or the second heat process comprise at least a heat process temperature, a heat process time, and a temperature increase/decrease value.
 13. A substrate processing program for execution on a computer, wherein the processing program, when executed, causes the computer to control a substrate processing system to perform a substrate processing method for forming a predetermined pattern on a substrate by executing a series of processes, which comprises a coating process for applying a resist liquid onto the substrate with an underlying film formed thereon, a first heat process for performing a heat process on the substrate after the coating process, a light exposure process for performing light exposure on a resist film in accordance with a predetermined pattern, a second heat process for promoting a chemical reaction in the resist film after the light exposure, a developing process for developing the resist film after the light exposure, and an etching process for etching the underlying film by use of a resist pattern formed by the developing process as a mask, the method comprising: measuring and checking a state of a resist pattern formed on the substrate after the developing process and outputting a first check result thus obtained; measuring and checking a state of a pattern formed on the substrate after the etching process and outputting a second check result thus obtained; using a correlation formula obtained from the first check result and the second check result to obtain a target value of the state of the pattern after the developing process from a target value of the state of the pattern after the etching process; and using a difference between the target value of the state of the pattern after the developing process and the first check result to set a condition for the first heat process and/or the second heat process so as to cause the state of the pattern after the etching process to be uniform on a surface of the substrate in a subsequent series of processes.
 14. A computer readable storage medium that stores the substrate processing program according to claim
 13. 